The present invention relates to semiconductor devices and techniques for manufacturing the semiconductor devices and in particular to a technique effectively applicable to SRAM (Static Random Access Memory) incorporated in an LCD (Liquid Crystal Display) driver or the like.
Japanese Unexamined Patent Publication No. 2007-43082 (Patent Document 1) discloses a semiconductor device having SRAM in which fluctuation in the characteristics of an MIS transistor caused by stress from an element isolation region is suppressed and a manufacturing method therefor. Specifically, this manufacturing method is such that an isolation insulating film is so formed that an active area of a first access transistor and a substrate contact area are integrated with each other as planarly viewed. A dummy gate electrode is formed over the area of a semiconductor substrate positioned between the active area of the first access transistor and the substrate contact area. This dummy gate electrode is electrically coupled with a p-type impurity region of the substrate contact area.
[Patent Document 1]    Japanese Unexamined Patent Publication No. 2007-43082